The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can prevent error caused when data are read from memory cells.
In the case of a semiconductor memory provided with dynamic memory cells, data stored in the memory cells are transferred to bit lines, in general after one word line has been selected on the basis of a row address and further voltage level at the word line has risen. Thereafter, a bit line sense amplifier corresponding to a column address becomes active to sense the bit lines, so that data are read from the memory cells.
In the above-mentioned dynamic memory, the word line driving circuit and bit line sense amplifier driving circuit are ordinarily arranged as peripheral blocks around the memory cells.
With the recent advance of a rapid increase in memory capacity, the length and the number of word lines through which read/write command signals are transmitted to the memory cells or bit lines through which signals read from the memory cells are transmitted increase more and more, with the result that the wiring resistance and load capacitance both increase. Therefore, there arise various problems in that the capability of the word line driving circuits relatively drops; the S/N ratio of the bit lines drops; the signals are delayed, etc.
To overcome these problems, it has been proposed that the memory cell areas be divided into several subareas. FIG. 1 shows an example thereof, in which the cell area on a memory chip is divided into 8 subareas so as to form a plurality of memory cell arrays 3a to 3h. Further, a row decoder, sense amplifier/column decoder, and a word line driving circuit are independently arranged for each memory cell array.
In FIG. 1, an address signal supplied from the outside is once stored in a row address buffer 1 and a column address buffer 2. The row address buffer 1 supplies a row address signal to the row decoders 4a to 4h of the respective memory cell arrays. In this case, if the outputs of the row decoders are the same, these row decoders can be used in common. The column address buffer 2 supplies a column address signal to the sense amplifier/column decoders 5a to 5h of the respective memory cell arrays.
FIG. 2 is a more detailed block diagram for assistance in explaining the operation of the memory cell arrays, in which n-piece memory cell arrays are arranged. A plurality of word line driving circuits 6a to 6n are arranged so as to correspond to the memory cell arrays 3a to 3n, respectively. The word line driving signals outputted from the circuits 6a to 6n are supplied to the word lines to activate these word lines themselves, respectively. Further, row decoders 4a to 4n for decoding a row address signal supplied from the row address buffer 1 are provided, respectively between the word line driving circuits 6a to 6n and the memory cell arrays 3a to 3n to select an address line to be driven by the row decoder.
As already described, since each bit line sense amplifier must be activated after the level of the selected word line has risen completely, the sense amplifier driving circuit 11 is activated being delayed by a predetermined delay time t1 through a delay circuit 10 after the word line driving circuit (e.g. 6a) has outputted a signal. The outputs of the sense amplifier driving circuit 11 are supplied to the sense amplifier/column decoders 5a to 5h of the respective arrays to drive the respective sense amplifiers. Here, the delay time t1 is determined long enough so that the operation of reading data to the bit lines can be completed after the level of the selected word line has risen.
FIG. 3 is a signal waveform diagram showing the relationship between the word line driving signal Wi, the sense amplifier driving signal SE, and the bit line potentials B, B when a data is read, in which the sense amplifier driving signal SE is outputted being delayed by a predetermined time period t1 after the word line driving signal Wi (solid curve) for selecting a word line has been generated.
When a word line driving signal is supplied to a word line selected by the row decoder, data stored at the memory cells connected to the word line are read to a pair of bit lines B and B. Since the potential at the bit line pair change slightly, a change in potential at the bit line pair is amplified by the sense amplifier, so that data reading operation can be completed. The row decoders 4a to 4n, the word line driving circuits 6a to 6n, the delay circuit 10 and the sense amplifier driving circuit 11 constitute a word line control means 100, as shown in FIG. 2.
Where the memory area is divided as described above, since the lengths of the word line and the bit lines for each memory cell can be reduced, it is possible to decrease the wiring resistance and capacitance, so that the load capacitance of each of the word line driving circuits 6a to 6n can be decreased and therefore the access speed can be increased.
In the prior art memory device, however, when the power supply voltage V.sub.CC and the ground voltage V.sub.SS fluctuate on the semiconductor chip in various way due to the operation of the internal circuits of the memory device, the timing at which the output Wi of the word line driving circuit is generated also fluctuates as shown by dot-dashed or dot-dot-dashed lines in FIG. 3. Since the delay time t1 is determined by the delay circuit 10 on the assumption that the respective arrays are operated under a stable supply voltage, there exists a problem in that the word line driving circuit generates the output after the basic delay time determined by the delay circuit 10. In this case, since the time interval between when the word line driving output is generated (being delayed excessively) to when the sense amplifier driving output is generated is reduced less than the predetermined optimum time t1, so that an erroneous sensing operation occurs with respect to the bit lines, thus resulting in a serious problem in that the memory cell data to be refreshed are destroyed. This problem is particularly marked in the case of multiport memory or field memory including a great number of circuits operated without synchronism with the word line driving circuits.